Various wireless systems including a mobile phone, wireless LAN, etc. use a wireless signal modulated by digital modulation format such as QPSK, etc. The RSA3408B Real-Time Spectrum analyzer manufactured by Tektronix, Inc., Beaverton, Oreg., U.S.A. is a signal analyzer suitable for analyzing such a modulated wireless signal.
FIG. 1 is a functional block diagram of an exemplary signal analyzer 10. An attenuator (ATT) 12 receives a signal under test to adjust the level appropriately. An analog down converter 20 has a mixer 14, a local oscillator (LO) 16 and a band pass filter (BPF) 18 to down-convert the input signal. An analog to digital converter 22 converts the down-converted signal to digital data according to a sampling clock from a clock generator 24. Note that a frequency of the sampling clock is well higher than the symbol rate of the received signal. A digital down converter (DDC) 26 further down-converts the digital data by digital calculation and separate them into I (Inphase) and Q (Quadrature) data. A trigger detector 30 receives the I and Q data (symbol data) of time domain data to detect I and Q data satisfying a trigger condition that a user presets concerning the time domain for providing a trigger signal to a memory controller 34. A fast Fourier transform (FFT) circuit 32 converts the I and Q data to frequency domain data to provide them to the trigger detector 30. The trigger detector 30 detects frequency domain data satisfying a trigger condition that the user preset concerning the frequency domain for providing a trigger signal to the memory controller 34. The memory controller 34 controls a data memory 28 to retain pre and post I and Q data around the trigger event of which time duration is set by the user when it receives the trigger signal. These blocks may be realized with hardware such as FPGA, ASIC, etc. to achieve real-time fast processes.
The IQ data of satisfying time and/or frequency domain trigger conditions in the data memory 28 is transferred to a microprocessor system with a CPU (Central Processing Unite) 36 through a bus 52. The microprocessor system may be known as a personal computer (PC) and the CPU 36 controls the signal analyzer 10 according to programs (software) stored in a hard disk drive (HDD) 42. The HDD 42 may be used to store a large amount of data that may not be always used. A memory 40, such as RAM, is used for a work area for the CPU 36 to read programs from the HDD 42.
A user can set up the signal analyzer 10 via an operation panel 44 that includes keys, knobs, and the like. Modulation formats, symbol rates, etc. used in mobile phone, wireless LAN are defined as standards so that the user sets up the settings depending on the signal under test. This allows starting the signal analysis smoother relative to “no-settings”. The parameters such as symbol rate may be replaced after when more accurate values are determined through the signal analysis.
A display device 38 provides visual information relating to the signal analysis and the user settings. An input/output port 46 is used for connecting an external keyboard 48, a pointing device 50, such as a mouse, and the like to the signal analyzer. They may be included as parts of the user interface of the signal analyzer 10. These blocks are coupled together via the bus 52.
The CPU 36 conducts the signal analysis concerning the IQ data from the data memory 28 according to the programs stored in the HDD 42. FIG. 2 is a functional block diagram of analyzing a digital modulation signal with software processes by the CPU 36, especially, it has recursive processes that detect the IQ data (symbol data) and generate an ideal signal to compare it with a measured signal for determining a modulation error. A carrier frequency correction block 62 corrects a frequency error of the IQ data due to the carrier frequency error by the digital down conversion at the DDC 26 by calculation. A measurement filter block 67 is a replica of characteristics of filters used in a receiver side and reduces noise components and intersymbol interference. A code demodulator 65 demodulates the IQ data into baseband data wherein the baseband data is generated as ideal one. This process uses that the IQ data are digital data and then it is relatively easy to assume the ideal values of the phases and amplitudes of the IQ data if the signal under test does not have significant distortions. A digital modulation block 66 modulates the ideal baseband data to generate IQ data of an ideal digital modulation signal. A reference filter block 67 is a filter of integrating filters of transmitter and receiver sides and eliminates a leak to an adjacent channel and intersymbol interference. An error detection block 64 compares the measured IQ data from a measurement filter 63 with the ideal IQ data from the reference filter bock 67 to detect an error at each IQ data. The error detection block 64 also generates a carrier frequency error signal and extracts a symbol timing signal.
The CPU 36 also conducts fast Fourier transform (FFT) to produce spectrum data from the IQ data to display it as a spectrum waveform on the display device 38. Though the FFT circuit 32 also conducts FFT, it is for real time detection of a frequency domain trigger by implementing the FFT circuit 32 as hardware. The FFT calculation by the CPU 36 takes a longer time and does not realize real time process but provides a high precision FFT result. Therefore, the spectrum data is produced by software process of the CPU 36 after the acquisition of the IQ data satisfying a trigger condition in the data memory 28.
The signal analysis by software process of the CPU 36 using the IQ data stored in the data memory 28 provides higher modulation accuracy and symbol table, etc. However, the information can not be used for generating a trigger since the process is after the acquisition. For example, if the modulation accuracy falls suddenly it would be desired to trigger at that time to investigate the cause. However, a current system does not allow such a trigger. The software process shown in FIG. 2 is complicated recursive one so that it is difficult to realize it using ASIC or FPGA in real time and at low cost.
US patent application publication 2009/0094495 by Torin discloses a trigger generator that detects a trigger using correlation between a reference modulation signal and amplitude and/or phase waveform of a modulation signal under test. The modulation error, however, can happen in various situations so that it is difficult to specify the amplitude and/or phase waveform in a target situation. Then, it is also difficult to trigger by detecting deterioration of modulation accuracy. As described, conventional technologies are not effective to trigger by detecting deterioration of modulation accuracy of a digital modulation signal under test.